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vitesse semiconductor corporation page 1 8/31/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc7122 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays g52155-0, rev. 2.1 features general description the VSC7122 is a quad port bypass circuit (pbc). four fibre channel pbcs are cascaded into a single part to minimize part count, cost, high frequency routing, and jitter accumulation. port bypass circuits are used to provide resiliency in fibre channel arbitrated loop (fc-al) architectures. pbcs are used within fc-al disk arrays to allow for resiliency and hot swapping of fc-al drives. a port bypass circuit is a 2:1 multiplexer with two modes of operation: normal and bypass. in nor- mal mode, the disk drive is connected to the loop. data goes from the 7122s l_son pin to the disk drive rx input and data from the disk drive tx output goes to the 7122s l_sin pin. refer to figure 2 for disk drive application. in bypass mode, the disk drive is either absent or non-functional and data bypasses to the next available disk drive. normal mode is enabled with a high on the sel pin and bypass mode is enabled by a low on the sel pin. direct attach fibre channel disk drives have an ?rc interlock?signal de?ed to con- trol the sel function. using a VSC7122 in a single loop of a disk array is illustrated in figure 2: ?isk array application? fc- al drives are all expected to be dual loop. the VSC7122 is cascaded in a manner such that all the 7122s inter- nal pbcs are used in the same loop. for dual loop implementations, two or more VSC7122s should be used. allocating each VSC7122 to only one of two loops preserves redundancy, prevents a single point of failure and lends itself to on-line maintainability. the VSC7122 is very similar to the vsc7121 except that lso+ outputs are all full power outputs identical to out. this is useful in passive backplanes to provide additional amplitude on long traces. 7122 block diagram ? supports ansi x3t11 1.0625 gbit/sec fc-al disk attach for resiliency ? fully differential for minimum jitter accumulation. ? quad pbcs in single package ? ttl bypass select ?high speed, pecl i/os referenced to v dd . ?0.35w typical power dissipation ?3.3v power supply ?44-pin, 10mm pqfp lsi1+ lsi1- lso1+ lso1- in+ in- out+ out- sel1 lsi2+ lsi2- lso2+ lso2- sel2 lsi3+ lsi3- lso3+ lso3- sel3 lsi4+ lsi4- lso4+ lso4- sel4 1 00 1 0 1 0 1 pbc1 pbc2 pbc3 pbc4
vitesse semiconductor corporation advance product information vsc712 2 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays page 2 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 8/31/98 g52155-0, rev. 2.1 the VSC7122 can be cascaded through the in and out pins for arrays of disk drives greater than 4. for disk arrays with a noninteger multiple of 4 disk drives, the unused pbcs can be hardwired to bypass with a external pulldown resistor. table 1 is a truth table detailing the data ?w through the VSC7122. figure 1 shows a timing diagram of the data relationship in the VSC7122. there are no critical timing (setup, hold, or delay) parameters for the VSC7122 as this part routes the serial data encoded with the baud clock that is extracted by a fibre channel receiver. the primary ac parameter of importance is the jitter or data eye degradation inserted by the port bypass circuit. the design of the VSC7122 minimizes jitter accummulation by using fully differential circuits. this provides for symmetric rise and fall delays as well as noise rejection. table 1: truth table figure 1: timing waveforms select state data outputs sel1 sel2 sel3 sel4 out so4 so3 so2 so1 llllinininin in l l l h si4 in in in in l l h l si3 si3 in in in l h l l si2 si2 si2 in in h l l l si1 si1 si1 si1 in hhhhsi4si3si2si1 in t 1 t 2 t jitter out+/- lso1+/- lso2+/- lso3+/- lso4+/- in+/- lsi1+/- lsi2+/- lsi3+/- lsi4+/-
vitesse semiconductor corporation page 3 8/31/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc7122 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays g52155-0, rev. 2.1 figure 2: disk array application 0 1 0 1 0 1 0 1 rx tx e_store lrc interlock fc-al disk drive rx tx e_store lrc interlock fc-al disk drive VSC7122 quad port bypass circuit rx tx e_store lrc interlock fc-al disk drive pulldown for bypass in absense of disk drive 7120 7120 optics or copper jbod normal normal normal bypass dual sc or db-9 7120 7120
vitesse semiconductor corporation advance product information vsc712 2 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays page 4 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 8/31/98 g52155-0, rev. 2.1 table 2: ac characteristics (over recommended operating conditions). table 3: dc characteristics (over recommended operating conditions). parameters description min. max. units conditions t 1 flow-through propagation delay rising edge to rising edge 7.0 ns delay with all circuits bypassed. 75 ohm load t 2 flow through propagation delay falling edge to falling edge 7.0 ns delay with all circuits bypassed. 75 ohm load. t sdr , t sdf serial data rise and fall time 300 ps. 20% to 80%, tested on a sample basis parameters description min typ max units conditions v ih(ttl) input high voltage (sel - ttl) 2.0 5.5 v i ih < 6.6 ma @ v ih = 5.5 v v il(ttl) input low voltage (sel - ttl) 0 0.8 v i ih(ttl) input high current (sel- ttl) 50 500 m av in = 2.4 v i il(ttl) input low current (sel - ttl) -500 m av in = 0.5 v v dd supply voltage 3.10 3.50 v v dd = 3.30v + 5% i dd supply current 150 ma outputs open, v dd = v dd max p d power dissipation 0.35 0.5 w outputs open, v dd = v dd max d v in receiver differential peak-to-peak input sensitivity, in+/- & l_sin+/- 300 2600 mvp-p ac coupled. internally biased at v dd /2 d v out50 output differential peak-to-peak voltage swing 1000 2200 mvp-p 50 w to v dd ?2.0 v d v out75 output differential peak-to-peak voltage swing 1200 2200 mvp-p 75 w to v dd ?2.0 v
vitesse semiconductor corporation page 5 8/31/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc7122 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays g52155-0, rev. 2.1 absolute maximum ratings (1) ttl power supply voltage, (v dd ) ..................................................................................................... 0.5v to +4v pecl dc input voltage, (v inp )............................................................................................. -0.5v to v dd +0.5v ttl dc input voltage, (v int ) ..........................................................................................................-0.5v to 5.5v dc voltage applied to outputs for high output state, (v in ttl )........................................ -0.5v to v dd + 0.5v ttl output current (i out ), (dc, output high)........................................................................................... 50ma pecl output current, (i out ), (dc, output high) ......................................................................................-50ma case temperature under bias, (t c ) ............................................................................................... -55 to +125 o c storage temperature, (t stg )......................................................................................................... -65 to + 150 o c maximum input esd .............................................................................................................. .................... 1500 v recommended operating conditions (2) power supply voltage, (v dd ) ...........................................................................................................+3.1v to 3.5v ambient operating temperature range, (t) .....................................................................................0 c to +70 c notes: 1) caution: stresses listed under ?bsolute maximum ratings?may be applied to devices one at a time without causing per- manent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability. 2) vitesse guarantees the functional and parametric operation of the part under ?ecommended operating conditions: except where speci?ally noted in the ac and dc parametric tables
vitesse semiconductor corporation advance product information vsc712 2 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays page 6 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 8/31/98 g52155-0, rev. 2.1 input structures two input structures exist in this part; ttl and high speed, differential inputs. the ttl inputs will inter- face with any ttl or 3.3v or 5v cmos outputs. the high speed, differential inputs are intended to be ac coupled per the fc-ph speci?ation. being ac coupled, the high speed, differential input buffers are biased at v dd /2. refer to figure 3 for high speed, differential input structure. figure 3: high speed, differential inputs (l_sin/in) because the VSC7122 output buffers are pecl outputs referenced to v dd , the high speed differential out- puts may not be direct coupled to the high speed differential inputs. one example of how to differentially cas- cade the two VSC7122 is shown in figure 4. figure 4: cascading two VSC7122 input + input- vdd/2 3.3k 3.3k vdd gnd 0 v +3.3 v 3.3k 3.3k VSC7122 out+ out - VSC7122 in+ in - v dd 191 124 124 191 .01 75 ohm board/termination example .01
vitesse semiconductor corporation page 7 8/31/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc7122 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays g52155-0, rev. 2.1 figure 5: pin diagram vss vss in+ vss l_so2+ l_so3- l_so2- vddp l_si3+ vss out+ l_so4+ out- vddp l_so1- l_so1+ vdd l_si4- vdd vss vss sel4 vdd in- vss vss sel3 sel1 sel2 vdd vddp l_si4+ vddp l_so4- vdd l_si2- l_si2+ l_si1+ l_si1- vss l_so3+ l_si3- vddp VSC7122 vss 1 3 5 7 9 11 33 31 29 27 25 23 13 15 17 19 21 43 41 39 37 35
vitesse semiconductor corporation advance product information vsc712 2 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays page 8 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 8/31/98 g52155-0, rev. 2.1 table 4: pin description pin # name description 9, 10 in-, in+ input - differential (biased at vdd/2). serial inputs from the downstream pbc port. 3, 4 l_si1-, l_si1+ input - differential (biased at vdd/2). serial input from the local transmitter on pbc port 1. 40, 41 l_si2-, l_si2+ input - differential (biased at vdd/2). serial input from the local transmitter on pbc port 2. 34, 35 l_si3-, l_si3+ input - differential (biased at vdd/2). serial input from the local transmitter on pbc port 3. 27, 28 l_si4-, l_si4+ input - differential (biased at vdd/2). serial input from the local transmitter on pbc port 4. 15-18 sel1, sel2, sel3, sel4 input - ttl. a low selects the ?ypass?mode causing the output of the previous port to propagate to next port or out. when high, this signal selects ?ormal? mode which routes the previous port to the local output, l_son, and routes the local input, l_sin, to the next port or out . 6, 7 l_so1-, l_so1+ output - differential serial output driving the local receiver corresponding to pbc port 1. 43, 44 l_so2-, l_so2+ output - differential serial output driving the local receiver corresponding to pbc port 2. 37, 38 l_so3-, l_so3+ output - differential serial output driving the local receiver corresponding to pbc port 3. 30, 31 l_so4-, l_so4+ output - differential serial output driving the local receiver corresponding to pbc port 4. 25, 24 out-, out+ output - differential serial output driving the upstream pbc port. 2, 14, 20-21, 32 vdd digital logic power supply. 3.3v supply for digital logic. 5, 26, 29 36, 42 vddp high-speed output power supply. 3.3v supply for pecl drivers. 1, 8, 11-13, 19, 22-23, 33, 39 vss ground. ground pins are physically attached to the die mounting surface, and are an important part of the thermal path. for best thermal performance, all ground pins should be connected to a ground plane, using multiple vias if possible.
vitesse semiconductor corporation page 9 8/31/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc7122 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays g52155-0, rev. 2.1 package information 44 34 0.102 max. lead coplanarity 1 33 23 22 12 g f ih 12 o typ 0.17 max. notes: 12 o typ k d a 0.25 j 0 o - 8 o 0.25 max. e 0.30 rad. typ. 0.20 rad. typ. 11 drawing not to scale. cavity up all units in mm unless otherwise noted. item mm tol. a 2.35 max d 2.00 +0.10 e 0.35 + .05 f 13.20 + .25 g 10.00 + .10 h 13.20 + .25 i 10.00 + .10 j 0.8 +.15 / -.10 k 0.80 basic 44-pin pqfp 10 x 10 mm
vitesse semiconductor corporation advance product information vsc712 2 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays page 10 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 8/31/98 g52155-0, rev. 2.1 package thermal characteristics the VSC7122 is packaged into a standard plastic quad ?tpack with an embedded, but unexposed thermal slug. this package adheres to industry standard eiaj footprints for a 10x10mm body, 44 lead pqfp. the pack- age construction is as shown in figure 6. the 44 pqfp with embedded slug has the thermal properties shown in table 5. this package allows the VSC7122 to operate with ambient temperatures up to 70 o c in still air. figure 6: package cross reference table 5: 44 pqfp thermal resistance moisture sensitivity level this device is rated with a moisture sensitivity level 3 rating. refer to application note an-20 for appro- priate handling procedures. symbol description value units q ca-0 thermal resistance from case to ambient, still air 50 o c/w q ca-100 thermal resistance from case to ambient, 100 lfpm air 43 o c/w q ca-200 thermal resistance from case to ambient, 200 lfpm air 39 o c/w q ca-400 thermal resistance from case to ambient, 400 lfpm air 36 o c/w q ca-600 thermal resistance from case to ambient, 600 lfpm air 34 o c/w lead die plastic molding compound insulator wire bond
vitesse semiconductor corporation page 11 8/31/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc7122 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays g52155-0, rev. 2.1 ordering information the order number for this product is formed by a combination of the device number and package type. marking information the package is marked with three lines of text as shown below (qm package): notice this document contains information about a new product during its fabrication or early sampling phase of development. the information in this document is based on design targets, simulation results or early prototype test results. characteristic data and other specications are subject to change without notice. therefore the reader is cautioned to con?m that this datasheet is current prior to design or order placement. warning vitesse semiconductor corporations product are not intended for use in life support appliances, devices or systems. use of a vitesse product in such applications without the written consent is prohibited. VSC7122 qm device type VSC7122 - 1.0625 gbits/sec port bypass circuit package type qm: 44 pin pqfp, 10x10mm body vitesse VSC7122qm package suf? part number pin identi?r ####aaaa lot tracking code date code
vitesse semiconductor corporation advance product information vsc712 2 quad port bypass circuit for 1.0625 gbit/sec fibre channel arbitrated loop disk arrays page 12 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 8/31/98 g52155-0, rev. 2.1

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